diff options
author | cinap_lenrek <cinap_lenrek@felloff.net> | 2020-12-11 15:24:35 +0100 |
---|---|---|
committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2020-12-11 15:24:35 +0100 |
commit | b1d1fa04b952d19064ecc9c4b0a6c07e39e71c3b (patch) | |
tree | 3fcd2329b069c015906a9b20a4b45ab6754a4347 | |
parent | 345e93dd4c5879655686edd282b859cf958360c4 (diff) | |
parent | fc0f08c65112e50a75d77042d8249b6bd15a3b76 (diff) | |
download | plan9front-b1d1fa04b952d19064ecc9c4b0a6c07e39e71c3b.tar.xz |
merge
-rw-r--r-- | sys/src/9/pc/memory.c | 12 | ||||
-rw-r--r-- | sys/src/9/pc/mtrr.c | 14 |
2 files changed, 13 insertions, 13 deletions
diff --git a/sys/src/9/pc/memory.c b/sys/src/9/pc/memory.c index f15f6e776..6df499728 100644 --- a/sys/src/9/pc/memory.c +++ b/sys/src/9/pc/memory.c @@ -383,16 +383,8 @@ e820scan(void) } } - /* - * Make sure RAM is set to writeback, - * but do a sanity check first checking - * that the kernel text is writeback. - * This is needed as some emulators (bhyve) - * set everything to uncached. - */ - s = mtrrattr(PADDR(KTZERO), nil); - if(s != nil && strcmp(s, "wb") == 0) - mtrrexclude(MemRAM, "wb"); + /* RAM needs to be writeback */ + mtrrexclude(MemRAM, "wb"); for(base = memmapnext(-1, MemRAM); base != -1; base = memmapnext(base, MemRAM)){ size = memmapsize(base, BY2PG) & ~(BY2PG-1); diff --git a/sys/src/9/pc/mtrr.c b/sys/src/9/pc/mtrr.c index a2dd475b0..f840b159d 100644 --- a/sys/src/9/pc/mtrr.c +++ b/sys/src/9/pc/mtrr.c @@ -305,11 +305,13 @@ getstate(State *s) vlong v; int i; - s->mask = physmask(); + if(rdmsr(MTRRCap, &s->cap) < 0) + return -1; - if(rdmsr(MTRRDefaultType, &s->def) < 0) + if((s->cap & (Capfix|Capvcnt)) == 0) return -1; - if(rdmsr(MTRRCap, &s->cap) < 0) + + if(rdmsr(MTRRDefaultType, &s->def) < 0) return -1; if(s->cap & Capfix){ @@ -332,6 +334,8 @@ getstate(State *s) return -1; } + s->mask = physmask(); + if(strcmp(m->cpuidid, "AuthenticAMD") != 0 || m->cpuidfamily < 15 || rdmsr(AMDK8SysCfg, &v) < 0 @@ -674,6 +678,10 @@ mtrr(uvlong base, uvlong size, char *tstr) if((new.type = str2type(tstr)) < 0) return "bad cache type"; + if(new.type == Writecomb + && (cpu0state.cap & Capwc) == 0) + return "write combining not supported"; + qlock(&mtrrlk); newstate = cpu0state; nr = getranges(&newstate, ranges, Nranges, &new); |