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| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2020-12-11 15:23:03 +0100 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2020-12-11 15:23:03 +0100 |
| commit | fc0f08c65112e50a75d77042d8249b6bd15a3b76 (patch) | |
| tree | 6c841cab8b86d19667255be1be5776356aaaf0dc | |
| parent | 658c994cfff444e0d473dbd312638c4f609fcc81 (diff) | |
| download | plan9front-fc0f08c65112e50a75d77042d8249b6bd15a3b76.tar.xz | |
pc, pc64: make sure write combining is supported in MTRR's before setting it
| -rw-r--r-- | sys/src/9/pc/mtrr.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/src/9/pc/mtrr.c b/sys/src/9/pc/mtrr.c index 7601ef543..f840b159d 100644 --- a/sys/src/9/pc/mtrr.c +++ b/sys/src/9/pc/mtrr.c @@ -678,6 +678,10 @@ mtrr(uvlong base, uvlong size, char *tstr) if((new.type = str2type(tstr)) < 0) return "bad cache type"; + if(new.type == Writecomb + && (cpu0state.cap & Capwc) == 0) + return "write combining not supported"; + qlock(&mtrrlk); newstate = cpu0state; nr = getranges(&newstate, ranges, Nranges, &new); |