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| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-05-17 18:56:34 +0200 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-05-17 18:56:34 +0200 |
| commit | 2235660f867148d6a5232ec42148af26b36560c7 (patch) | |
| tree | a17f5e8f3a629f1fdcfbaa66006b3a48d08cea68 | |
| parent | 5c5c1b666681cb3e8d2adbfe2ade22fe8447ffc2 (diff) | |
| download | plan9front-2235660f867148d6a5232ec42148af26b36560c7.tar.xz | |
bcm64: no need to flush instruction cache when switching TTBR0
| -rw-r--r-- | sys/src/9/bcm64/l.s | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/sys/src/9/bcm64/l.s b/sys/src/9/bcm64/l.s index c40dd8fc1..9690bffa6 100644 --- a/sys/src/9/bcm64/l.s +++ b/sys/src/9/bcm64/l.s @@ -331,8 +331,7 @@ TEXT setttbr(SB), 1, $-4 MSR R0, TTBR0_EL1 DSB $ISH ISB $SY - - B cacheiinv(SB) + RETURN /* * TLB maintenance operations. |