From 2235660f867148d6a5232ec42148af26b36560c7 Mon Sep 17 00:00:00 2001
From: cinap_lenrek <cinap_lenrek@felloff.net>
Date: Fri, 17 May 2019 18:56:34 +0200
Subject: bcm64: no need to flush instruction cache when switching TTBR0

---
 sys/src/9/bcm64/l.s | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/sys/src/9/bcm64/l.s b/sys/src/9/bcm64/l.s
index c40dd8fc1..9690bffa6 100644
--- a/sys/src/9/bcm64/l.s
+++ b/sys/src/9/bcm64/l.s
@@ -331,8 +331,7 @@ TEXT setttbr(SB), 1, $-4
 	MSR	R0, TTBR0_EL1
 	DSB	$ISH
 	ISB	$SY
-
-	B	cacheiinv(SB)
+	RETURN
 
 /*
  * TLB maintenance operations.
-- 
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