basic pci and ahci support

Signed-off-by: Anna (navi) Figueiredo Gomes <navi@vlhl.dev>

1 files changed, 63 insertions, 0 deletions

diff --git a/include/ahci.h b/include/ahci.h
new file mode 100644
index 0000000..61da329
--- /dev/null
+++ b/include/ahci.h
@@ -0,0 +1,63 @@
+#ifndef _SATA_H_
+#define _SATA_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+struct ahci_port {
+	uint32_t clb;       // 0x00, command list base address, 1K-byte aligned
+	uint32_t clbu;      // 0x04, command list base address upper 32 bits
+	uint32_t fb;        // 0x08, FIS base address, 256-byte aligned
+	uint32_t fbu;       // 0x0C, FIS base address upper 32 bits
+	uint32_t is;        // 0x10, interrupt status
+	uint32_t ie;        // 0x14, interrupt enable
+	uint32_t cmd;       // 0x18, command and status
+	uint32_t rsv0;      // 0x1C, Reserved
+	uint32_t tfd;       // 0x20, task file data
+	uint32_t sig;       // 0x24, signature
+	uint32_t ssts;      // 0x28, SATA status (SCR0:SStatus)
+	uint32_t sctl;      // 0x2C, SATA control (SCR2:SControl)
+	uint32_t serr;      // 0x30, SATA error (SCR1:SError)
+	uint32_t sact;      // 0x34, SATA active (SCR3:SActive)
+	uint32_t ci;        // 0x38, command issue
+	uint32_t sntf;      // 0x3C, SATA notification (SCR4:SNotification)
+	uint32_t fbs;       // 0x40, FIS-based switch control
+	uint32_t rsv1[11];  // 0x44 ~ 0x6F, Reserved
+	uint32_t vendor[4]; // 0x70 ~ 0x7F, vendor specific
+};
+
+struct hba_mem {
+	// 0x00 - 0x2B, Generic Host Control
+	uint32_t cap;     // 0x00, Host capability
+	uint32_t ghc;     // 0x04, Global host control
+	uint32_t is;      // 0x08, Interrupt status
+	uint32_t pi;      // 0x0C, Port implemented
+	uint32_t vs;      // 0x10, Version
+	uint32_t ccc_ctl; // 0x14, Command completion coalescing control
+	uint32_t ccc_pts; // 0x18, Command completion coalescing ports
+	uint32_t em_loc;  // 0x1C, Enclosure management location
+	uint32_t em_ctl;  // 0x20, Enclosure management control
+	uint32_t cap2;    // 0x24, Host capabilities extended
+	uint32_t bohc;    // 0x28, BIOS/OS handoff control and status
+
+	// 0x2C - 0x9F, Reserved
+	uint8_t rsv[0xA0-0x2C];
+
+	// 0xA0 - 0xFF, Vendor specific registers
+	uint8_t vendor[0x100-0xA0];
+
+	// 0x100 - 0x10FF, Port control registers
+	struct ahci_port ports[]; // 1 ~ 32
+};
+
+struct disk {
+	uint32_t id;
+	uint64_t block_count;
+	struct ahci_port *port;
+};
+
+void probe_port(struct hba_mem *abar);
+bool read(volatile struct ahci_port *port, uint64_t offset, uint32_t count, uint16_t buf[256 * count]);
+struct disk *get_disk(int id);
+
+#endif