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| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2020-11-21 16:26:46 +0100 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2020-11-21 16:26:46 +0100 |
| commit | 2594b99629957d8ce380157e9af4a5feff86c5fe (patch) | |
| tree | 7ae97a752d8a552c26837b6612e63cb8ef53a39c /lib/cmap/bbmap | |
| parent | e6684dbfda0507565f44967680b850b35a5b4f93 (diff) | |
| download | plan9front-2594b99629957d8ce380157e9af4a5feff86c5fe.tar.xz | |
pc, pc64: new MTRR code supporting AMD TOM2 MSR and fixed mtrr ranges
The new MTRR code handles overlapping ranges
and supports AMD specific TOM2 MSR.
The format in /dev/archctl now only shows
the effective cache ranges only, without
exposing the low level registers.
Diffstat (limited to 'lib/cmap/bbmap')
0 files changed, 0 insertions, 0 deletions