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| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2017-01-22 21:08:28 +0100 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2017-01-22 21:08:28 +0100 |
| commit | 885d41dd7b87c41cb618140d50dd23501b6d4279 (patch) | |
| tree | 900aa30709d6dd17df4fba70ef2553d009fffaa9 | |
| parent | 6cb359cc00bdc8204b011db46b8746c446f2c4de (diff) | |
| download | plan9front-885d41dd7b87c41cb618140d50dd23501b6d4279.tar.xz | |
sgi: get rid of timerset(0) case
| -rw-r--r-- | sys/src/9/sgi/clock.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/sys/src/9/sgi/clock.c b/sys/src/9/sgi/clock.c index 0355e66f5..c7a0da440 100644 --- a/sys/src/9/sgi/clock.c +++ b/sys/src/9/sgi/clock.c @@ -148,14 +148,10 @@ timerset(Tval next) { long period; - if(next == 0) + period = next - fastticks(nil); + if(period < m->minperiod) + period = m->minperiod; + else if(period > m->maxperiod - m->minperiod) period = m->maxperiod; - else { - period = next - fastticks(nil); - if(period > m->maxperiod) - period = m->maxperiod; - else if(period < m->minperiod) - period = m->minperiod; - } wrcompare(rdcount()+period); } |