diff options
| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2018-10-08 07:05:28 +0200 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2018-10-08 07:05:28 +0200 |
| commit | 2fecc5789efc1cf1f0343890a363adc7ccaaeda5 (patch) | |
| tree | a4380030871948b76935d016d06f7b3ab2f3fbfe | |
| parent | a71a57f8f26f2eec86266e2f7febf9c839781df4 (diff) | |
| download | plan9front-2fecc5789efc1cf1f0343890a363adc7ccaaeda5.tar.xz | |
usbxhci: delay after reset, preserve reserved bits in legacy status control register in handoff()
when clering smi enable bits in the legacy control/status register,
preserve the reserved bits. clear the RW1C bits.
linux code claims intel xhci controller needs a 1ms delay before
accessing any register after reset.
| -rw-r--r-- | sys/src/9/pc/usbxhci.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/sys/src/9/pc/usbxhci.c b/sys/src/9/pc/usbxhci.c index 9c8253a2e..e03f27418 100644 --- a/sys/src/9/pc/usbxhci.c +++ b/sys/src/9/pc/usbxhci.c @@ -397,9 +397,12 @@ handoff(Ctlr *ctlr) r[0] |= 1<<24; /* request ownership */ for(i = 0; (r[0] & (1<<16)) != 0 && i<100; i++) tsleep(&up->sleep, return0, nil, 10); - r[0] &= ~(1<<16); /* in case of timeout */ } - r[1] = 0; /* disable SMI interrupts */ + /* disable SMI interrupts */ + r[1] = (r[1] & (7<<1 | 255<<5 | 7<<17)) | 7<<29; + + /* clear BIOS ownership in case of timeout */ + r[0] &= ~(1<<16); } static void @@ -462,6 +465,7 @@ init(Hci *hp) tsleep(&up->sleep, return0, nil, 10); ctlr->opr[USBCMD] = HCRST; + delay(1); for(i=0; (ctlr->opr[USBSTS] & (CNR|HCH)) != HCH && i<100; i++) tsleep(&up->sleep, return0, nil, 10); |