backend/drm: set "max bpc" property based on pixel format

Since 1d581656c756 ("backend/drm: set "max bpc" to the max") we
set the "max bpc" property to the maximum value. The kernel driver
is supposed to clamp this value depending on hardware capabilities.

All kernel drivers lower the value depending on the GPU capabilities.
However, none of the drivers lower the value depending on the DP-MST
link capabilities. Thus, enabling a 4k@60Hz mode can fail on some
DP-MST setups due to the "max bpc" property.

Additionally, it's not a good idea to unconditionally set "max bpc"
to the max. A high bpc consumes more lanes and more clock speed,
which means higher power consumption and the busy lanes cannot be
used for something else (e.g. other data transfers on a USB-C cable).

For now, let's tie the "max bpc" to the pixel format of the buffer.
Introduce a heuristic to make "high bit-depth buffer" a synonym of
"I want the best quality".

This is not perfect: a "max bpc" higher than 8 might be desirable
for pixel formats with a color depth of 8 bits, for instance when
the color management KMS properties are used. But we don't really
support that yet, so let's leave this for later.

Closes: https://github.com/swaywm/sway/issues/7367

1 files changed, 1 insertions, 1 deletions

diff --git a/include/backend/drm/drm.h b/include/backend/drm/drm.h
index e93b5eaf..01971e52 100644
--- a/include/backend/drm/drm.h
+++ b/include/backend/drm/drm.h
@@ -107,7 +107,7 @@ struct wlr_drm_connector {
 	char name[24];
 	drmModeConnection status;
 	uint32_t id;
-	uint64_t max_bpc;
+	uint64_t max_bpc_bounds[2];
 	struct wlr_drm_lease *lease;
 
 	struct wlr_drm_crtc *crtc;