From 5b8b5884f4eacd26b1e234c5abedd1615d895003 Mon Sep 17 00:00:00 2001 From: Ori Bernstein Date: Sat, 23 Jan 2021 20:36:09 -0800 Subject: 5l: fix shifts by zero on arm32, we can do one of 4 shifts by a constant: reg<<(0..31) reg>>(1..32) ((u32int)reg)>>(1..32) reg ROT (0..31) There's no way to encode a 0 bit right shift, so when encoding reg>>0, flip it to the equivalent nop reg<<0, which can be encoded. --- sys/src/cmd/5l/asm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sys/src/cmd/5l/asm.c b/sys/src/cmd/5l/asm.c index 1d3ecc68b..54f3343e1 100644 --- a/sys/src/cmd/5l/asm.c +++ b/sys/src/cmd/5l/asm.c @@ -785,7 +785,10 @@ PP = p; case 8: /* sll $c,[R],R -> mov (R<<$c),R */ aclass(&p->from); - o1 = oprrr(p->as, p->scond); + if((p->as == ASRL || p->as == ASRA) && instoffset == 0) + o1 = oprrr(ASLL, p->scond); + else + o1 = oprrr(p->as, p->scond); r = p->reg; if(r == NREG) r = p->to.reg; -- cgit v1.2.3